DDR Controller

Key Features


  • + 8 Slave DDR Ports
  • 16/32-bit DDR SDRAM data interface
  • Independent slave device configuration
  • Independent transaction queuing
  • Auto Write Leveling feature
  • Programmable burst length
  • Automatic refresh
  • Mode register programming
  • Automatic row activation
  • Full synthesizable
Overview
Architecture
Applications
Resources

The DDR controller was designed as an SoC interface for industry standard DDR devices. The hardware architecture of the controller has autonomous features which simplifies control at the application level. In addition it is also capable of controlling, and configuring all features of standard DDR devices, such as Write Leveling, bank refreshing and row activation. Setup and configuration for the device is very simple and requires only a few steps, software initialization routines and documentation is provided to get application developers off to a quick start.