Chameleon-QSII

Key Features


  • 32 Advanced RISC
  • Custom Instruction
  • Microprogrammable
  • 5 Stage Pipeline
  • Advanced ALU 2X Throughput
  • Small Footprint
  • Branch Prediction
  • Single Precision Floating Point Unit
  • Pipeline Integrated FPU
Overview
Architecture
Applications
Resources
Tools
The QSII processor is based on the QSI, with several substantial improvements. The execution unit is an ALU which can handle advanced instructions, such as fixed point square root, inverse square root, multiply-add and multiply-subtract instructions. In addition to the advanced instruction set, the advanced ALU architecture allows for accelerated performance compared to the rest of the cpu, for example performance increase doubles on multiply, divide and, square root instructions. These hardware accelerators allows the compiler to create more efficient machine code. The uPC was designed to target embedded applications, which require a higher throughput than the QSI and an advanced instruction set.