Chameleon-QSIII

Key Features


  • 32 Advanced RISC
  • Custom Instruction
  • Microprogrammable
  • 5 Stage Pipeline
  • Single Cycle ALU
  • Branch Prediction
  • Single Precision Floating Point Unit
  • Pipeline Integrated FPU
  • Advanced Math Instructions
    • Sqrt
    • Mult/Add
    • Mult/Sub
Overview
Architecture
Applications
Resources
Tools
QSIII is a 32 bit RISC microprocessor (uPC) optimized for embedded systems, such as FPGAs, CPLD and ASIC technologies. While there is a standard instruction set architecture (ISA), the instruction set is application specific and can be micro-coded for custom applications. The processor is based on a single cycle execution, five stage pipeline architecture. The execution unit is divided into two units an advanced ALU and a single precision Floating Point Unit (FPU). In addition this processor has an advanced optimization feature which allows the compiler to create more efficient machine code. The uPC was designed to target embedded applications which require a high throughput and a very low latency between uPC and peripheral ASICs, and additional computational abilities such as a floating point math.