Chameleon-QSIV

Key Features


  • 32 Advanced RISC
  • Custom Instruction
  • Microprogrammable
  • 5 Stage Pipeline
  • Single Cycle ALU
  • Execution Over Clocking 2X performance
  • ALU & FPU Parallel Processing
  • Branch Prediction
  • Single Precision Floating Point Unit
  • Pipeline Integrated FPU
  • Advanced Math Instructions
    • Sqrt
    • Mult/Add
    • Mult/Sub
Overview
Architecture
Applications
Resources
Tools
QSIV is a 32 bit 1st generation superscalar microprocessor (uPC) optimized for embedded systems, such as FPGAs, CPLD and ASIC technologies. While there is a standard instruction set architecture (ISA), the instruction set is application specific and can be micro-coded for custom applications. The processor is based on a single cycle execution, five stage pipeline architecture. The execution unit is divided into two units an ALU and a single precision Floating Point Unit (FPU). The processor is capable of out of order instruction processing, fixed point and floating point math operations can be handled independently and concurrently. In addition this processor has an even more advanced ISA which allows the compiler to create more efficient machine code. The uPC was designed to target embedded applications which require a high throughput and advanced computational abilities such as a floating point and some DSP operations.